selected work · 4 builds · all open source
Things I've built
Hardware and systems projects, from CPU design to VLSI layout — one of them
on its way back from the foundry. Everything here started as a blank schematic.
01
[ SystemVerilog · SIMT · CGRA · Cadence · TSMC 180nm ]
MiniDICE
A GPGPU-style architecture that keeps the familiar SIMT programming model but
replaces the traditional SIMD backend with a 4×4 coarse-grained reconfigurable
array. The design supports up to 16 threads, mapping computation spatially across
16 processing elements — preserving the programmability of GPU-like execution
while giving it a dataflow-oriented backend.
- Values move directly through the CGRA fabric instead of repeatedly travelling through a large centralized register file
- Investigates how general-purpose parallel workloads map onto a more energy-conscious compute fabric
- Taken from RTL to GDS through a complete ASIC flow in Cadence — synthesis, physical design, timing analysis, signoff, and physical verification
- Final GDS submitted for fabrication in TSMC 180nm; silicon comes back in fall 2026
02
[ SystemVerilog · Computer Architecture · ModelSim · ARM ]
ARM-Based 5-Stage Pipeline CPU
Designed and implemented a pipelined processor supporting the ARM instruction set.
The CPU features a complete 5-stage pipeline with data forwarding, achieving
improved performance through accelerated branching techniques.
- Full 5-stage pipeline with forwarding and accelerated branching
- Comprehensive testing with ARM benchmarks and ModelSim
03
[ VLSI Design · Cadence Virtuoso · HSPICE · 45nm ]
16×13 Register File
Custom VLSI layout of a register file featuring a 4-to-16 wordline decoder,
16×13 DFF storage array, and 16:1 multiplexer network. Designed in 45nm technology
with careful attention to power, performance, and area.
- Full-custom layout in 45nm CMOS technology
- Complete power, performance, and area testing with HSPICE
- DRC and LVS verified design
04
[ SystemVerilog · FPGA · Hardware Design · ModelSim ]
Snakes and Apples
The classic Snake game implemented entirely in hardware on an FPGA board —
custom logic for game state management, collision detection, and real-time
rendering on a 16×16 LED matrix with PS/2 keyboard input. No software involved.
- Hardware game logic with dynamic snake growth and collision detection
- 16×16 LED matrix display controller
- PS/2 keyboard interface for player input